The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for providing improved on-chip networks for flexible three-dimensional chip integration.
A three-dimensional integrated circuit is a chip with two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit. A three-dimensional integrated circuit chip is a single chip in which all components on the layers communicate with on-chip signaling, whether vertically or horizontally. In contrast to three-dimensional integrated circuits, three dimensional packaging involves a plurality of chips packaged into a single package but which are not integrated with each other into a single circuit. With three dimensional packages, communication must be made through off-chip mechanisms due to the fact that the chips are not integrated with each other.
Three-dimensional packaging saves space by stacking separate chips in a single package. However, three-dimensional integrated circuits provide many benefits including a smaller footprint (since more functionality fits into a smaller space), faster speed (the average wire length is much shorter), reduced power consumption, heterogeneous integrated (circuit layers can be built with different processes, different technologies, and may be supplied by different vendors), and increased circuit security (the stacked structure hinders attempts to reverse engineer the circuitry).
While three-dimensional integrated circuits provide these various benefits, three-dimensional integrated circuits lack flexibility with regard to the interconnect layer used to handle communication between the integrated layers of the three-dimensional integrated circuit. That is, the interconnect layer has a single pattern of wiring that is optimized for a single type of integrated circuit chip and which is inefficient or unable to support other integrated circuit chip designs. Moreover, because of this inflexibility of the interconnect layer, the compute and storage layers are tightly coupled with a fixed matching between them using the interconnect layer.